The tip effect is used in certain devices, especially to increase the field effect.
Thus, it is known, in charge-storage nonvolatile memories, to create tips on the polysilicon floating gate, so as to facilitate the injection of carriers into the upper gate.
It is possible in this regard to cite U.S. Pat. Nos. 5,783,473, 6,410,957 and 6,635,922 as well as the following articles:
“An Analytical Model for Optimization of Programming Efficiency and Uniformity of Split Gate Source-Side Injection Superflash Memory”, Huinan Guan, IEEE Transactions on Electron Devices, vol. 50, No. 3, March 2003,
“A Novel 3 Volts-Only, Small Sector Erase, High Density Flash E2PROM”, Sohrab Kianian et al., 1994 Symposium on VLSI Technology Digest of Technical Papers, 1994 IEEE,
“Tunneling Phenomenon in Superflash® Cell”, A. Kotov et al., 2002 IEEE Nonvolatile Memory Technology Symposium, p. 110-115.
The formation of the tips of the floating gate comprises an oxidation of the polysilicon of this floating gate.